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<title>VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values </title></head>
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<h1>VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.66.0F3A.W0 56 /r ib</p>
<p>VREDUCEPS xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Perform reduction transformation on packed single-precision floating point values in xmm2/m128/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F3A.W0 56 /r ib</p>
<p>VREDUCEPS ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Perform reduction transformation on packed single-precision floating point values in ymm2/m256/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F3A.W0 56 /r ib</p>
<p>VREDUCEPS zmm1 {k1}{z}, zmm2/m512/m32bcst{sae}, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512DQ</td>
<td>Perform reduction transformation on packed single-precision floating point values in zmm2/m512/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register under writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>Imm8</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Perform reduction transformation of the packed binary encoded single-precision FP values in the source operand (the second operand) and store the reduced results in binary FP format to the destination operand (the first operand) under the writemask k1.</p>
<p>The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transfor-mation can be expressed as:</p>
<p>dest = src – (ROUND(2<sup>M</sup>*src))*2<sup>-M</sup>;</p>
<p>where “Round()” treats “src”, “2<sup>M</sup>”, and their product as binary FP numbers with normalized significand and bi-ased exponents.</p>
<p>The magnitude of the reduced result can be expressed by considering src= 2<sup>p</sup>*man2, where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent</p>
<p>Then if RC = RNE: 0&lt;=|Reduced Result|&lt;=2<sup>p-M-1</sup></p>
<p>Then if RC ≠ RNE: 0&lt;=|Reduced Result|&lt;2<sup>p-M</sup></p>
<p>This instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision Exception, which is imm8[3]=1), no precision exception is reported.</p>
<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<p>Handling of special case of input values are listed in Table 5-21.</p>
<p><strong>Operation</strong></p>
<p>ReduceArgumentSP(SRC[31:0], imm8[7:0])</p>
<p>{</p>
<p>// Check for NaN</p>
<p>IF (SRC [31:0] = NAN) THEN</p>
<p>RETURN (Convert SRC[31:0] to QNaN); FI</p>
<p>M (cid:197) imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted</p>
<p>RC (cid:197) imm8[1:0];// Round Control for ROUND() operation</p>
<p>RC source (cid:197) imm[2];</p>
<p>SPE (cid:197) 0;// Suppress Precision Exception</p>
<p>TMP[31:0] (cid:197) 2<sup>-M</sup> *{ROUND(2<sup>M</sup>*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2<sup>M </sup>as standard binary FP values</p>
<p>TMP[31:0] (cid:197) SRC[31:0] – TMP[31:0]; // subtraction under the same RC,SPE controls</p>
<p>RETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand</p>
<p>}</p>
<p><strong>VREDUCEPS</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask* THEN</p>
<p>IF (EVEX.b == 1) AND (SRC *is memory*)</p>
<p>THEN DEST[i+31:i] (cid:197) ReduceArgumentSP(SRC[31:0], imm8[7:0]);</p>
<p>ELSE DEST[i+31:i] (cid:197) ReduceArgumentSP(SRC[i+31:i], imm8[7:0]);</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] = 0</p>
<p>FI;</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VREDUCEPS __m512 _mm512_mask_reduce_ps( __m512 a, int imm, int sae)</p>
<p>VREDUCEPS __m512 _mm512_mask_reduce_ps(__m512 s, __mmask16 k, __m512 a, int imm, int sae)</p>
<p>VREDUCEPS __m512 _mm512_maskz_reduce_ps(__mmask16 k, __m512 a, int imm, int sae)</p>
<p>VREDUCEPS __m256 _mm256_mask_reduce_ps( __m256 a, int imm)</p>
<p>VREDUCEPS __m256 _mm256_mask_reduce_ps(__m256 s, __mmask8 k, __m256 a, int imm)</p>
<p>VREDUCEPS __m256 _mm256_maskz_reduce_ps(__mmask8 k, __m256 a, int imm)</p>
<p>VREDUCEPS __m128 _mm_mask_reduce_ps( __m128 a, int imm)</p>
<p>VREDUCEPS __m128 _mm_mask_reduce_ps(__m128 s, __mmask8 k, __m128 a, int imm)</p>
<p>VREDUCEPS __m128 _mm_maskz_reduce_ps(__mmask8 k, __m128 a, int imm)</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Invalid, Precision</p>
<p>If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).</p>
<p><strong>Other Exceptions</strong></p>
<p>See Exceptions Type E2, additionally</p>
<table>
<tr>
<td>#UD</td>
<td>If EVEX.vvvv != 1111B.</td></tr></table></body></html>